warnings - Lattice Diamond: Setting up a clock -

i'm working on learning verilog , working cplds , i'm stuck. code wrote toggles led, keep getting warnings during synthesis.

//toggles led on , off after 1000000 clock cycles  module ledon( led, clk );  output led; reg led;  input clk ; wire clk;  reg [31:0] count; wire count_max = 32'd1_000_000;  assign count_nxt = (count >= count_max) ? 32'd0 : count + 32'd1; assign led_state_nxt = (count == count_max) ? ~led : led;  @(posedge clk)  begin     count <= count_nxt;     led <= led_state_nxt;  end  endmodule 

i these warnings:

@w: mt420 |found inferred clock ledon|clk period 1000.00ns. please declare user-defined clock on object "p:clk"
warning - map: c:/documents , settings/belo/desktop/ledon2/ledon2.lpf (4): error in frequency net "clk" 2.080000 mhz ;
warning - map: preference parsing results: 1 semantic error detected
warning - map: there errors in preference file, "c:/documents , settings/belo/desktop/ledon2/ledon2.lpf".
warning - map: there semantic errors in preference file, "c:/documents , settings/belo/desktop/ledon2/ledon2.prf".

my lpf file looks this:

block resetpaths ; block asyncpaths ; locate comp "led" site "41" ; frequency net "clk" 2.08 mhz ; 

so know how fix these clock warnings?

i'm not sure if line: "wire count_max = 32'd1_000_000;" synthesisable. might being ignored except in simulation (this depend on tool chain - it's not synthesisable asic, fpga ... maybe!!).

the line count>= count_max comparing count 0 (and not count max) , being optomised away (see warnings). why it's managed synthesise not anything.

there multiple solutions. 1) use parameter instead (it's const in c++ or #define in c):

parameter count_max = 32'd1_000_000; 

2) use smaller counter , toggle when overflows

reg [16:0] count; // counts 131,072 cycles  assign led_next = (count == 0 ? ~led : led); @(posedge clk) begin     count <= count + 1;     led <= led_next; end